In hardware design it is sometimes necessary to implement a binary add or subtract function where one of the inputs has a skewed arrival time. If the least significant bits of either of the operands arrives the latest, a conventional adder will not be able to execute concurrently with any other prior computation. The total latency of the system (defined to be the adder and the calculation which is skewing the arrival of an input) will need to include a full adder delay.
An example of having a skewed input adder is the exponent update during normalization of a floating point number. The fraction shift amount needs to be subtracted from the input exponent. The input exponent is known prior to any bits of the shift amount given that the shift amount is determined from a leading zero detect of the data being normalized. Also, the shift amount's most significant bits are available earlier than the least significant. A method and system for performing exponent update in parallel with shifting the fraction during normalization of a floating point number has been disclosed by the present inventors in commonly assigned U.S. patent application Ser. No. 08/414,072, filed Mar. 31, 1995 which is hereby incorporated by reference.
As mentioned, however, in hardware design there are many situations where late arriving data can introduce additional latency. There is a need, therefore, for an improved adder/subtractor which does not introduce latency due to late arriving data.